1. Field of the Invention
The present invention relates to a duty cycle correction circuit for providing a clock signal with a half duty cycle or a one-Nth duty cycle.
2. Description of the Related Art
Generally, a delay locked loop (DLL) is used in a synchronous semiconductor memory device, such as a double data rate synchronous dynamic random access memory (DDR SDRAM), to perform synchronization between an internal clock signal and an external clock signal of the synchronous semiconductor memory device. A DDR SDRAM employs a rising edge and a falling edge of a clock signal to process data so as to increase the operation speed of data. As the operational speed of the DDR SDRAM is increased, performance of the DDR SDRAM is greatly affected by the DLL. Therefore, since design margin decreases with an increase of duty error, having a correct duty cycle of the internal clock is important. Reliable data transmission is achieved when the duty cycle is equivalent to 50%, and a duty cycle correction circuit applied to the DLL is required for ensuring sufficient design margin of the duty cycle.
U.S. Pat. No. 7,576,581 provides a circuit for correcting a duty cycle. The circuit configured to correct a duty cycle includes a digital conversion block, a duty ratio information analyzing block, and a duty ratio control block. An output clock signal having a duty cycle equivalent to 50% is obtained by mixing phases of rising and falling clock signals rclk and fclk with a phase mixing unit, wherein the signal fclk is generated by controlling a falling edge of a selected delayed clock signal and the signal rclk is generated by controlling a falling edge of an input clock signal. U.S. Pat. No. 7,428,286 provides an apparatus for correcting duty cycle of clock signals used in semiconductor memories. The duty cycle correction apparatus comprises a delay line block, a DCC phase mixer, a phase mixer controller and a phase comparator. The DCC phase mixer corrects a duty cycle of an external clock signal to 50% by mixing an external inversion clock signal and a delay line output inversion clock signal. The aforementioned circuits all require a phase mixer to correct the duty cycle of a clock signal. However, the phase mixer comprises a plurality of drivers to implement pull-up and pull-down functions, and therefore consumes a large amount of power and requires a large silicon area.
Accordingly, there is a need to provide a circuit and method for correcting the duty cycle of a clock signal. The corrected duty cycle can be employed in a synchronous semiconductor memory device, such as a DDR SDRAM, to improve operation efficiency.